Portable electronic devices are ubiquitous accoutrements in modern life. Cellular telephones, smartphones, satellite navigation receivers, e-book readers and tablet computers, wearable computers (e.g., glasses, wrist computing), cameras, and music players are just a few examples of the many types of portable electronic devices in widespread use. Portable electronic devices are powered by batteries—either replaceable batteries such as alkaline cells, or rechargeable batteries such as NiCd, NiMH, LiOn, or the like. In either case, the useful life of portable electronic devices is limited by available battery power, which decreases in proportion to the length of use of the device, and the level of power consumption during that use.
Trends in portable electronic device design include higher levels of circuit integration, shrinking device form factors (and hence smaller batteries), increasing functionality requiring more memory and more powerful processors, and wireless connectivity—all of which have made power management a critical area of optimization for portable electronic device designers.
One approach to power management is the definition of a plurality of Operating Performance Points (OPP) for at least some integrated circuits (IC). An OPP may define the minimum supply voltages to be applied to various parts of the chip (e.g. logic or memory arrays), the current requirements, operating frequencies, and the like. In general, an OPP defines the minimum power requirements for stable operation of the IC for some operating state or use case. The system transitions between predefined OPPs in response to, e.g. user activity or incoming communications, switching to lower-power OPPs whenever possible to reduce overall power consumption.
Power management circuits are an increasingly sophisticated part of modern portable electronic device system design. Power management circuits may optimize power consumption by the use of switched mode power supplies (SMPS). As known in the art, a SMPS delivers power from a source, such as a battery, to a load, such as one or more ICs, by switching discrete quanta of charge through switching transistors into or out of an energy storage component such as an inductor or capacitor. Various parameters of the SMPS may be configured to provide optimum supply voltages for each OPP. An optimum supply voltage is one that is sufficient for stable operation of the IC, but which minimizes current consumption. The parameters that may be adjusted include SMPS switching frequency, switching mode (e.g., PWM, PSK, PFM), and output stage scaling.
Every SMPS has at least one output stage, classically one PMOS and one NMOS transistor connected in series between the battery and ground, with the energy storage component connected between the common transistor node and the load. When the SMPS is delivering high output current, efficiency is maximized by maximizing the size of the switching transistors, to minimize conduction losses due to the transistor resistance (RON). On the other hand, when the output current demand is small, efficiency is maximized by using small switching transistors, to minimize the gate drive losses associated with charging and discharging the gate capacitances. A flexible approach, in systems where the load current may vary (such as a system that switches between OPPs), is to configure a plurality of output stages, each comprising a pair of switching transistors, and selectively enable an appropriate number of the stages, to deliver the desired output current to the load(s). This raises the challenge of how to select the optimal number of output stages depending the loading, to optimize the SMPS efficiency. Several approaches to this selection are known in the art.
A straightforward approach is to measure output current and adjust the number of output stages accordingly. In the prior art this method is variously known as on-line, adaptive, or dynamic scaling. This approach often suffers from timing issues. If the number of output stages is changed too rapidly, the SMPS may react to ripple on the loading current and cause instability, and/or unwanted spectral components at the output. If the number of output stages is changed too slowly, efficiency or/and performance may suffer if the loading changes more rapidly than expected. One example of rapid changes in current loading is when changing OPPs. A proportional-integral-derivative (PID) control loop would be one compromise to satisfy the worst case requirements; however, in that case efficiency cannot be maximized. For more information, consult the paper by Oliver Trescases, et al., “A Digitally Controlled DC-DC Converter Module with a Segmented Output Stage for Optimized Efficiency,” published in the Proceedings of the 18th International Symposium on Power Semiconductor Devices & ICs, 2006, which is incorporated herein by reference in its entirety.
Another known approach is to define a look-up table (LUT) that contains an output stage configuration for each OPP. Since proper operation of the electronic device is more important than maximizing its battery life, the stored output stage configurations must cover the worst case current consumption. This must be estimated taking into account factors such as operating conditions, temperature, aging, process variation of the IC consuming the power, different use cases, and the software version running on the IC consuming the power. Additionally, conservative design would mandate a margin to ensure the required quality level. As a result, the output stage configuration stored in the LUT for a given OPP is almost certainly too conservative, and in actual operation the SMPS will not approach optimal efficiency.
The Background section of this document is provided to place embodiments of the present invention in technological and operational context, to assist those of skill in the art in understanding their scope and utility. Unless explicitly identified as such, no statement herein is admitted to be prior art merely by its inclusion in the Background section.